The present invention relates to a logic circuit using a complementary type MOS circuit (hereinafter, referred to as a C-MOS circuit) which is formed of a P-channel MOS field effect transistor (hereinafter, referred to as a P-MOS FET) and an N-channel MOS field effect transistor (hereinafter, referred to as an N-MOS FET), and more particularly to an improvement for preventing malfunctions due to noise superposed on power voltage. 2. Description of the Prior Art:
The C-MOS circuits have a basic construction such that a P-MOS FET and an N-MOS FET are connected in series between power voltage terminals. This basic C-MOS circuit has a feature of very small power consumption, and, therefore, have been widely used in many logic circuits. According to one of such logic circuits, an input signal is processed in several stages of circuit blocks using the basic C-MOS circuit.
The logic circuits are generally formed in an N-type silicon substrate. The N-MOS FET's are formed in a P-well region formed in the silicon substrate, while the P-MOS FET's are directly formed in the silicon substrate. A power voltage V.sub.DD is applied to the back surface of the silicon substrate. Another power voltage V.sub.SS is applied to a portion of the P-well on the upper surface of the silicon substrate, causing a resistance based on the lateral component of the P-well and inserted in series between the N-MOS FET and the power voltage V.sub.SS. Here, a resistance based on the vertical component of the silicon substrate is negligibly small. If the P-well resistance in the fore stage of circuit blocks is larger than that in the following stage, the circuit may produce malfunctions in response to noise superposed on the power voltage V.sub.SS.
The malfunctions will now be explained. It is assumed that when the output of the force stage is on low level of the power voltage V.sub.SS, the power voltage V.sub.SS lowers suddenly by a noise. In the transition period of voltage, the source voltage of the N-MOS FET in the fore stage becomes higher than the source voltage of the N-MOS FET in the following stage. As a result, the voltage of the output of the fore stage, that is, the voltage of the input voltage of the following stage becomes higher than the source voltage of the N-MOS FET. If the difference between the input voltage and the source voltage is higher than the threshold voltage of the N-MOS FET in the following stage, the N-MOS FET in the following stage, unexpectedly turns on. This unexpected operation resulted in a malfunctions of the logic circuit.